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RFD15N06LE, RFD15N06LESM
Data Sheet April 1999 File Number
4079.1
15A, 60V, 0.065 Ohm, ESD Rated, Logic Level, N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49165.
Features
* 15A, 60V * rDS(ON) = 0.065 * 2kV ESD Protected * Temperature Compensating PSPICETM Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFD15N06LE RFD15N06LESM PACKAGE TO-251AA TO-252AA BRAND F15N6L F15N6L
Symbol
D
NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 9A to the part number, i.e. RFD15N06LESM9A.
G
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICETM is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD15N06LE, RFD15N06LESM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD15N06LE, RFD15N06LESM 60 60 10 15 Refer to Peak Current Curve Refer to UIS Curve 72 0.48 -55 to 175 2 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . ESD Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC kV
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA TO-251 and TO-252 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 48V, ID = 15A, RL = 3.20 Figures 20, 21 TEST CONDITIONS ID = 250A, VGS = 0V, Figure 13 VGS = VDS, ID = 250A, Figure 12 VDS = 48V, VGS = 0V VGS = 10V ID = 15A, VGS = 5V VDD = 30V, ID = 15A, RL = 2.0, VGS = 5V, RGS = 2.5 Figures 10, 18, 19 TC = 25oC TC = 150oC MIN 60 1 TYP 11 40 30 18 39 21 0.95 855 240 75 MAX 2 1 50 10 0.065 77 75 49 26 1.20 2.08 100 UNITS V V A A A ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
VDS = 25V, VGS = 0V, f = 1MHz Figure 14
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr TEST CONDITIONS ISD = 15A ISD = 15A, dISD/dt = 100A/s MIN TYP MAX 1.5 80 UNITS V ns
6-150
RFD15N06LE, RFD15N06LESM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 0 25
Unless Otherwise Specified
20
ID, DRAIN CURRENT (A)
15
10
5
50
75 100 125 TC, CASE TEMPERATURE (oC)
150
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 100 101
PDM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200 100 ID, DRAIN CURRENT (A)
IDM, PEAK CURRENT CAPABILITY (A)
TC = 25oC, TJ = MAX RATED
200
TC = 25oC VGS = 10V
100 VGS = 5V
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150
100s
10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
10ms 100ms DC 60 100
THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RFD15N06LE, RFD15N06LESM Typical Performance Curves
50 IAS, AVALANCHE CURRENT (A) STARTING TJ = 25oC ID, DRAIN CURRENT (A) STARTING TJ = 150oC 10
Unless Otherwise Specified (Continued)
30 25 20 15 10 5 VGS = 2.5V 10 0 0 1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 6.0
VGS = 10V VGS = 5V VGS = 4V
TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX.
VGS = 3.5V
VGS = 3V
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
30
VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
-55oC
25oC
rDS(ON), DRAIN TO SOURCE
200
25 20
ON RESISTANCE (m)
175oC
150 ID = 15A ID = 7.5A 100 ID = 30A
15
10
ID = 3.75A 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
5
0
0
1.5 3 4.5 VGS, GATE TO SOURCE VOLTAGE (V)
6
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
250 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = 30 V, ID =15A, RL= 2.00 200 SWITCHING TIME (ns) td(OFF) 150 tr
2.5 VGS = 5V, ID = 15A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 2.0
1.5
100 tf 50 td(ON) 0 0 10 20 30 40 50
1.0
0.5 -80
-40
0
40
80
120
160
200
RGS, GATE TO SOURCE RESISTANCE ()
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
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RFD15N06LE, RFD15N06LESM Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.0
Unless Otherwise Specified (Continued)
1.2
ID = 250A
1.1
0.8
1.0
0.6
0.9
0.4 -80
-40
0
40
80
120
160
200
0.8 -80
-40
TJ, JUNCTION TEMPERATURE (oC)
0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
1200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
60 VDD = BVDSS 45 RL =4.00 IG(REF) = 0.44mA VGS = 5V 30 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (ms) I G ( REF ) 80 -----------------------I G ( ACT ) 2.50 VDD = BVDSS 3.75 5.00 VGS , GATE TO SOURCE VOLTAGE (V)
1000 C, CAPACITANCE (pF) CISS 800 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS 200 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 CRSS
600
400
VDS , DRAIN TO SOURCE VOLTAGE (V)
15
1.25
0
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
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RFD15N06LE, RFD15N06LESM Test Circuits and Waveforms
(Continued)
tON td(ON) RL VDS VGS VGS
+
tOFF td(OFF) tr tf 90%
VDS
90%
0V RGS DUT
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
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RFD15N06LE, RFD15N06LESM PSPICE Electrical Model
SUBCKT RFD15N06LE 2 1 3 ; CA 12 8 2.50e-9 CB 15 14 2.4e-9 CIN 6 8 7.70e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.18 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.77e-9 LSOURCE 3 7 2.98e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 14.52e-3 RGATE 9 20 2.6 RLDRAIN 2 5 10 RLGATE 1 9 27.7 RLSOURCE 3 7 29.8 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 20.05e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1 LGATE 10 RLDRAIN RSLC2 RSLC1 51 + 5 ESLC 51 50 ESG 6 8 + RDRAIN 16 EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE 7 S1A 12 13 8 S1B 13 CA EGS + 6 8 EDS S2A 15 14 13 S2B CB + 5 8 8 RVTHRES 14 IT SOURCE 3 RLSOURCE RBREAK 17 18 RVTEMP 19 VBAT + 22 21 MMED + EBREAK 17 18 MWEAK DBODY DBREAK 11
rev 5/13/95
LDRAIN DPLCAP 5 DRAIN 2
EVTEMP RGATE + 18 9 20 22 DESD1 91 DESD2
RLGATE
VBAT 22 19 DC 1 ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*72),5))} .MODEL DBODYMOD D (IS = 6.5e-13 RS = 1.20e-2 TRS1 = 1.75e-3 TRS2 = 5.08e-6 CJO = 7.45e-10 TT = 4.61e-8 M = 0.46) .MODEL DBREAKMOD D (RS = 1.28e-1 TRS1 = -2.15e-3 TRS2 = 1.05e-5) .MODEL DESD1MOD D (BV = 12.7 TBV1 = 0 TBV2 = 0 RS = 35 TRS1 = 1.2e-6 TRS2 = 0) .MODEL DESD2MOD D (BV = 12.7 TBV1 = 0 TBV2 = 0 RS = 0 TRS1 =0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 4.32e-10 IS = 1e-30 N = 10 M = 0.54) .MODEL MMEDMOD NMOS (VTO = 1.60 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.60) .MODEL MSTROMOD NMOS (VTO = 1.93 KP = 26.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.39 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.0 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.76e-4 TC2 = 5.11e-7) .MODEL RDRAINMOD RES (TC1 = 1.30e-2 TC2 = 4.49e-5) .MODEL RSLCMOD RES (TC1 =3.00e-3 TC2 = 6.00e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -1.43e-3 TC2 = -6.72e-6) .MODEL RVTEMPMOD RES (TC1 = -9.91e-4 TC2 = 1.02e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.85 VOFF = -1.85) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.85 VOFF = -4.85) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.35 VOFF = 1.65) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF = -1.35 .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
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RFD15N06LE, RFD15N06LESM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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